1. Field of the Invention
The present invention relates to a semiconductor storage device equipped with a floating gate, particularly floating gate type erasable and programable read only memory cell (abbreviated EPROM). Particularly the present invention relates to an improved floating gate type EPROM structure, and a method of making the same. Also, the present invention relates to an electrically erasing an writing method for such floating type EPROM.
2. Description of the Prior Art
Such floating gate type EPROM is known as a memory device permitting the quick writing of data. This memory structure is discussedin the paper "A DSA-type Non-Volatile Memory Transistor with self-Aligned Gates" by M. Kikuchi et al, Proceedings of the 9th Conference on Solid-State Devices, 1977, and is disclosed and referred to as "Diffusion-Self-Alignment" (abbreviated DSA) in the paper "New Proposal for Scaling Rule; Compatibleness of Reliability with Excellent Performance" by K. Yoshikawa et al, January issueof the magazine "Nikkei Microdevice", 1990. The structure and operation of a conventional floating gatetype EPROM cell will be described below with reference to FIG. 1. As shown, it is built in a P-type semiconductor substrate 11 of silicon and is isolated by an area 14. An underlying channel stopper 20 extends on the bottom surface of the isolation area 14. A first gate insulating film 15 is applied to the top surface of the semiconductor substrate 11. A floating gate 12 is formed on the first gate insulating film 15, and a second gate insulating film 16 is applied to the top surface of the floating gate 12. A control gate 13 is formed on the second gate insulating film 16. An N-type source diffusion layer 19 extends from the isolation area 14 and ends at a location below one edge of the floating gate 12 in the semiconductor substrate 11. A second N-type drain diffusion layer 18 extends from the isolation area 14 and the channel stopper 20, and ends at a location below somewhat inside the other edge of the floating gate 12 in the semiconductor substrate 11. Finally, a first P-type drain diffusion layer 17 lies under the second N-type drain diffusion layer 18, extending from the isolation area 14 and the channel stopper 20 and ending at a location below the other edge of the floating gate 12 ahead of the terminal end of the second N-type drain diffusion layer 18 in the semiconductor substrate 11. It should be noted that the first drain diffusion layer 17 is heavily doped with a P-type impurity particularly in a concentration of 10 to 100 times higher than the semiconductor substrate 11 and that the so heavily doped first drain diffusion layer 17 completely encircles the second N-type drain diffusion layer 18. This will be again referred to later in describing the central feature of the present invention. Thanks to the extension of the first P-type drain diffusion layer 17 ahead of the second N-type drain diffusion layer 18, there exist an abundant of holes at a location below the edge of the floating gate 12 with the result that an electric field of increased strength appears just below the floating gate 12, thereby enhancing creation of hot electrons and accordingly increasing the writing speed.
The complete enclosure of the second N-type drain diffusion layer 18 by the first P-type drain diffusion layer 17, however, increases the electrostatic junction capacitance of these diffusion layers. Thus, an array of such memory cells will have a large total capacitance to cause an adverse effect on the operation of the memory array, that is, the increasing of the access and writing time. Also, it should be noted that the first P-type drain diffusion layer 17 is heavily doped with a P-type impurity, extending from the channel stopper 20, and that the channel stopper 20 is heavily doped with a P-type impurity in a concentration several orders of magnitude thicker than the P-type semiconductor substrate 11 With this arrangement the overlapping area of these heavily doped layers 17 and 20 will be still increasingly abundant in holes, and this hole-abundant region will be the cause for substantially lowering the breakdown voltage of the drain diffusion layer, and substantially deteriorating the diode characteristic of the drain diffusion layer with respect to the semiconductor substrate 11. In the end disadvantageously the writing speed will be lowered.
In the writing-in operation electrons will be injected into the floating gate of the memory device. The charging of the floating gate with electrons, however, will be adversely affected by surrounding parasitic positive ions. Specifically, the information retaining capability of the memory device will be appreciably lowered in a relatively short time by partial cancellation of electrons with surrounding parasitic positive ions.